1. Field of the Invention
This invention relates to a multilevel controller and more particularly for such controller for a cache memory interface between a data processor and another processing system each of which have different operating speeds as well as memory addressing requirements.
2. Description of the Prior Art
In the interfacing of two different data processing systems, particularly of different performance rates, a number of incompatabilities are encountered. Such incompatabilities include differences in memory access times, the different clock frequencies at which the respective processors are operated, different command structures and memory addressing capabilities of the respective processors.
The present invention is directed toward interfacing one or more commercially available entry level data processors such as Burroughs B5900 with a large multiprocessing system, which entry level data processors serve as auxiliary processors for the purposes of handling off-loaded chores and also maintenance routines where required. The performance and throughput of the system is thus greatly enhanced by relieving the main data processing units of such tasks. Incompatabilities must be resolved due to the fact that the large multiprocessing system clock rate can be different than that of the entry level data processor, and the main memory system is 128 times the capacity of the entry level system. This in turn, requires memory control words which contain more bits than does the entry level system. Further, because the main memory system is a hundred twenty-eight times that for which the entry level data processor was designed, its access time is larger than that of the entry level processor.
The system interface of the present invention resolves these incompatabilities in a number of ways. The system interface resolves the difference in memory access capabilities by providing a cache mechanism for storing a number of data and code words at a time, which words are fetched from the main memory system while the auxiliary processor is working with the data and code words currently in the cache mechanism. The use of such a cache mechanism as a buffer between a large but relatively slow memory system and a data processor and the provision for accessing a large back-up memory should a requested data element not be present in the cache mechanism is disclosed in the Barton U.S. Pat. Nos. 3,292,152 and No. 3,292,153. Such techniques are employed in many commercially available data processing systems such as the IBM System 360/370 series.
In addition, the system interface anticipates and prefetches from the main memory system those segments or "pages" of code which would normally be next required by the auxiliary processor. The system interface is also adapted to convert the auxiliary processor's commands into memory control words as well to synchronize the clocks of the main memory system and the auxiliary processor respectively.
It will be appreciated from the above, that the system interface must control a number of different actions occurring between the auxiliary processor and the main memory system, which actions are requested and occur independently of one another, and since the auxiliary processor and the main memory system with which it communicates have independent controls, the system interface requires a multilevel control unit to control the various independent operations without denying access to portions of cache memory currently being used by the auxiliary processor.
It is then, an object of the present invention to provide an improved system interface between an auxiliary processor and a large multiprocessing system having different data rates, memory capacity and control word format.
It is another feature of the present invention to provide such a system interface with a multilevel control unit to control independently initiated actions across the interface.
It is still another object of the present invention to provide such a multilevel control unit which nevertheless synchronizes independently requested actions across the interface.